The invention is particularly but not exclusively concerned with sensing in a memory device in which memory cells are formed by insulated gate transistors such as a PROM, EPROM or FLASH EPROM. However, the reference circuit can be used in any situation where a reference level is required.
When providing a reference level for sensing, one criteria which should be met is that the reference level can be supplied to a plurality of sensing circuits without altering the reference level.
For flash memories, the level required for sensing during a read operation is normally set at a fraction of the sum of the signals generated by a programmed cell and an erased cell, for example a half. It is advantageous to generate this reference level such that it is dependent on the characteristics of other identical flash memory cells. While it would be possible to provide a reference flash memory cell having a threshold voltage altered to provide a signal level which is, for example, halfway between the signals generated by a programmed cell and an erased cell, such a cell could not be used to generate a reference current for sensing both programmed and erased cells the reference signal will not be accurately maintained in the case of normal variations in the supply level Vcc, and hence the voltage applied to the gate of the reference cell. It is therefore desirable to use as a reference cell a cell having a threshold voltage sufficiently below the gate voltage to guarantee adequate sensing current, i.e. an erased cell.